ULVAC Received the "Best Interactive Presentation Award" at the IEEE 74th ECTC, the World's Largest International Conference in the Field of Electronic Packaging

ULVAC, Inc. presented a paper titled "A novel plasma etching technology of RIE-lag free TSV and dicing processes for 3D chiplets interconnect" at the IEEE 74th Electronic Components and Technology Conference (ECTC)^*1 held in Denver, Colorado, from Tuesday, May 28 to Friday, May 31, 2024, and was awarded the "Best Interactive Presentation Award." This award is one of four awards given to presentations recognized as academically and technically outstanding from among 391 general presentations (252 oral and 139 poster presentations).
The award ceremony was held at the IEEE 75th ECTC on May 28, 2025.

Details of the Award and Technology

In our poster presentation titled "A novel plasma etching technology of RIE-lag free TSV and dicing processes for 3D chiplets interconnect," we reported on a new dry etching technology for TSVs (Through Silicon Vias) with high aspect ratios and smooth sidewalls, as well as plasma dicing technology, and a new processing technology called the Dual TSV process, all utilizing our proprietary Dual frequency ICP (Inductively Coupled Plasma) technology. This achievement was highly evaluated and led to the award. This technology enables the silicon dry etching process to be utilized under a wider range of conditions than ever before, and its application to next-generation 3D chiplet integration technology^*2 is highly anticipated.

"Dual-frequency ICP" is a technology that generates an inductively coupled plasma (ICP) by applying RF (Radio Frequency) currents of different frequencies to the same space. By using this etching equipment that utilizes the characteristic plasma, we can achieve new processing methods in dry etching of silicon that were difficult with conventional methods. This technology plays a critical role in next-generation 3D chiplet integration technology. This technology eliminates the "scallop" problem in the Bosch process, which is a conventional TSV formation process. As a result, we have achieved an unprecedented level of smooth side wall shape and high precision processing with an aspect ratio (ratio of diameter to depth) of 11. Furthermore, by applying this technology to plasma dicing, silicon die singulation with extremely smooth sidewalls has been achieved. With this achievement, we have made a new proposal to improve conventional processing methods.

The Dual TSV process is a new method realized by utilizing dual-frequency ICP technology. In this technology, dual-frequency ICP is applied to "cyclic etching," in which film deposition and etching are alternately repeated, and the coverage of the deposited film can be adjusted. By utilizing this characteristics, we have proposed an unconventional Dual TSV process, in which TSVs of different diameters are simultaneously processed to the same depth.

Future Prospects

In recent years, as AI technology has been introduced, the amount of data processed worldwide has increased exponentially, and energy consumption has increased in proportion to this. As a result, there is an urgent need to improve the information processing capabilities of CPUs and HBM (High Bandwidth Memory) for data centers and to increase the energy efficiency of their energy consumption. This technology is attracting attention as an important technology that supports the high performance and high efficiency of these devices, and it is expected to be widely applied in industry.

Taking this award as an opportunity, we will further promote technical exchanges with domestic manufacturers and accelerate the practical application of technology. We will also continue to promote technological innovation that contributes to the semiconductor industry as a whole, with the aim of achieving greater sophistication, diversification and energy efficiency to meet customer needs.

*1 The IEEE Electronic Components and Technology Conference (ECTC) is the world's largest academic conference in the field of electronics packaging technology and a very important conference for sharing the latest research results on packaging technology. In 2024, the conference marked its 74th edition, and a total of 36 presentations were given on the theme of 3D chiplet integration, co-packaged optics, reliability, quantum computing, AI, healthcare and wearable devices, attracting cutting-edge researchers from many countries for lively discussions.

*2 3D Chiplet Integration Technology is a packaging technology that arranges, stacks and connects multiple semiconductor chips (chiplets) manufactured using different processes in the most suitable combination. Compared to conventional 2D packaging technology, it achieves higher density, and is attracting attention as a technology that will further accelerate the evolution of integrated circuits based on Moore's Law proposed by Gordon Moore. This technology makes it possible to build high-performance, low-power systems while making the most of the functions of each chip. In particular, there are high expectations for its potential in next-generation processors and high-performance computing for AI and data centers.

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