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Power electronics play an essential role in the construction of smart cities and as part of the solution to global warming. Power electronics are used to convert and control electric power in various applications, such as electric trains, automobiles, solar cells, and air conditioners. Power devices, the key component of power electronics, are required to deliver high performance, such as low power loss and high switching speed.
Figure 1 illustrates the relationship between various power device applications and semiconductor materials used to manufacture the power devices in the power electronics market. The horizontal axis denotes operating frequency, and the vertical axis denotes switching power. For the last several decades, Si has been mainly used as a semiconductor material for power device production.
However, power devices based on Si are approaching their theoretical performance limits determined by the physical properties of Si. Expectations for a major breakthrough in power electronics using Si-based power devices are all but gone. As a substitute for Si, wide-band-gap semiconductors (SiC, GaN, and diamond) are promisingmaterials. In particular, SiC has found wider application in various areas than other materials, and the development of SiC-based devices has been advancing. Compared with Si, SiC has about three times the band gap, about ten times the dielectric breakdown field, and a higher BFOM (Baliga’s Figure of Merit) by two orders of magnitude.
BFOM is an index indicating the performance of power devices, and this higher BFOM suggests that operating resistance, an essential factor in achieving low power loss, can be reduced by a factor of 2001 1）－3）.
In order to launch SiC devices into the market, our Advanced Electronics Equipment Division has developed an ion implantation system and an activation annealing system for SiC production, and our Institute of Semiconductor & Electronics Technologies has developed a SiC process and mass production technologies. In addition, we teamed up with TPEC (Tsukuba Power-Electronics Constellations) to develop a mass production process for SiC devices, to conduct verification tests on SiC devices, and
to refine the equipment.
TPEC was inaugurated in April 2012, as a base organization for promoting the development and spread of mass production technologies for SiC power semiconductors in industry-government-academia collaboration. From 2010 to 2012, the National Institute of Advanced Industrial Science and Technology, Fuji Electric Co., Ltd., and ULVAC, Inc. cooperatively conducted an Industry Innovative Research Initiative entitled,“ Research on Trial Production for SiC Device Mass Production and Verification of System Application.” TPEC inherited this activity and has been continuing the research.
This article mainly describes the results of tests performed in the process of developing mass production
technologies for SiC devices, reporting the process of ion implantation and activation annealing and the results of characteristic evaluation of modules constructed by combining prototype devices, SBDs (Schottky-Barrier Diodes) and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).
2.1 Key technology for SiC process
While the SiC device process has a major advantage in that technologies for the Si process can be used for it, one reason SiC devices are harder to produce than Si devices is that the diffusion coefficient of SiC materials is so small.
Due to their small diffusion coefficient, the thermal diffusion technology used for the Si process is not applicable to the SiC device process. Accordingly, we use ion implantation technology instead of thermal diffusion technology and implant ions at several levels of energy to form a box profile. In the Si process, room-temperature implantation is generally used. On the other hand, in the SiC device process, implantation needs to be performed with the SiC substrate maintained at a high temperature in order to suppress 3C-SiC growth during the activation annealing
process after implantation. Otherwise, 3C-SiC will reduce the channel mobility of the SiC devices.
In the conventional Si process, activation can be achieved at approximately 1,000℃, whereas in the SiC
process, high-temperature annealing at 1,600℃ or higher is required due to the strength of the bond of SiC molecules.
In addition, in a high-temperature process, the evaporation of Si atoms from SiC molecules causes rough
surfaces, leading to a reduction in channel mobility. To prevent this phenomenon from occurring, the carbon cap process is needed to suppress the evaporation of Si atoms.
The activation annealing technology needs to satisfy these requirements. Unlike oxide-layer (SiO2) formation from a Si layer in the Si process, in the gate oxide process of the SiC process, an oxide layer is formed from a SiC layer. Consequently, C atoms remain in the interface which raises the interface state
density. To eliminate this problem, studies on various methods for decreasing the interface state density have been actively carried out. 4H-SiC, which is used for device production, has two C-planes, a silicon face (0001) and a carbon face (000-1). The silicon face and carbon face of 4H-SiC have different dangling bonds and therefore their surfaces and interfaces exhibit different physical properties. For example, thermal oxidation of the carbon face progresses several times faster than that of the silicon face. Accordingly, conditions for forming a gate oxide layer need to be optimized separately for each crystal face. Generally, dry oxidation using oxygen and nitridation using nitrogen monoxide are used for the treatment of the silicon face, and wet oxidation and H2 annealing (mentioned later) are used for treatment of the carbon face.
Table 1 lists the above-mentioned key process technologies used for the production of SiC power devices (SBDs, planar MOSFETs, and trench MOSFETs). Device performance is determined more by production processes than by device combinations and physical properties. Accordingly, Table 1 shows device regions and the important processes that are applied to the device regions to determine device performance related to dielectric strength and power loss (particularly on-resistance).
The ion implantation and activation annealing technologies are key process technologies common to all SBDs, planar MOSFETs, and trench MOSFETs.
The above-mentioned key process technologies are used for various device regions requiring higher dielectric- strength performance, for example, the device edge regions and Schottky contact interfaces of SBDs and the device edge regions and P-well regions of planar/trench MOSFETs. In the process of fabricating trench MOSFETs, in addition to these process technologies, plasma etching technology is also used to form trench gate regions.
The above-mentioned key processes are also used for various portions requiring higher performance related to power loss, for example, the contact regions of SBDs and the contact regions, P-well regions, gate oxide layers, and SiC interfaces of planar/trench MOSFETs.
2.2 Process system
This article introduces some mass-production models that are particularly important for SiC device production. These models have been created from the base systems used at TPEC.
The IH-860DSIC mass-production ion implantation system (Figure 2) provides the following features.
a) High throughput
b) High-temperature implantation using an electrostatic chuck (up to 500℃)
c) Dual end station switchable between room-temperature implantation and high-temperature implantation
d) Multiple energy ion implantation for forming box profiles (maximum energy: 860 keV, operation using double charged ions)
We conducted implantation under conditions for a box profile (30–300 keV; 5×1018 cm－3) followed by activation annealing at 1,600-2,000 ℃ . Subsequently, we conducted measurement by SIMS (Secondary Ion Mass Spectrometry) and verified that the IH-860DSIC performs both highenergy and high-accuracy implantation (in terms of energy and dose amount) as shown in its simulation. We also observed that the dopant profile does not vary with the annealing temperature (1,600-2,000℃). This suggests that the dopant does not drive in by thermal diffusion.